Problem with SV Interfaces in Quartus

It will be interesting to hear what they say.

I spent probably way to much time looking at it, but best I can tell, yes it looks like Quartus is strictly treating the instantiation in your top level module as a bundle of wires.

If you go down with one or more submodules which reference that instance in their port list, then those submodules can use an 'initial' statement on the interface member and it works like you expect.

The treatment seems similar to how you would have connected submodules with wires in the top level and output registers in the submodule port declarations, which maybe is how the tool author assumed it would be used.

e.g. this works

interface my_interface;
        logic      some_byte;
	
	function void tick;
		some_byte = some_byte + 1'b1;
	endfunction
	
	function void init;
		some_byte = 8'b1010_1010;
	endfunction
endinterface
module fpga_tester(
	input wire clk,
   output  logic          test_byte
);
	my_interface test_interface();
	counter u0
	(
		.clk ( clk ),
		.x   (test_interface)
	);
			
       assign test_byte = test_interface.some_byte;
endmodule
module counter
(
	input wire clk,
	my_interface x
);
	 initial 
		x.init();
	always @(posedge clk)
		x.tick();
endmodule