Forum Discussion
Altera_Forum
Honored Contributor
12 years agoThank you for replying.
I think I may have misunderstood what interfaces are. I went through some tutorials that basically described them as a more advanced version of a struct including bidirectional ports and assignments/functions/tasks. Based on that, I thought an interface could “contain” a register in the same way a struct or module does. ModelSim was fine with that mentality, but I think Quartus is taking the perspective that an interface is literally just a bundle of wires. That is why the initial statement works as expected for structs, but not for interfaces. There’s no initial statement for wires. I found a verbose workaround based on the assumption that registers are only allowed outside of interfaces. In this case I treated the interface as being only a wire and added a continuous assignment from the interface wire to a register outside of the interface.interface my_interface;
logic some_byte;
endinterface
module fpga_tester(
output logic test_byte
);
my_interface test_interface(); //Create an interface instance.
assign test_byte = test_interface.some_byte; //Top level output comes from interface.
logic sample_value; //Test "register"
initial sample_value = 8'b1010_1010; //Initialize
assign test_interface.some_byte = sample_value; //Continuous assignment to interface of register value
endmodule This approach seems like it will lead to a lot of redundant code in practice, but Quartus at least builds it into hardware with behavior that matches simulation. On the subject of complaints from Quartus, instantiating an interface always causes Quartus to tell me the interface is nothing but dangling pins. That happens even if the synthesized design works as expected. I can put in example interface code from Doulos or even Altera, and Quartus will still complain about how all the pins are dangling. I found previous forum posts about the dangling pin warning where it looked like the consensus was to just ignore it.