Problem with SV Interfaces in Quartus

That is part of what I’m saying my issues are. I was under the impression that an interface is an entity like a module, not merely a collection of wires. I am specifically trying to use an interface like a module in the examples. I thought that was allowed, and ModelSim was okay with it. I didn't see why it wouldn't be synthesizable that way.

I can expand the original problematic example by creating a couple modules that use the interface to show that passing the interface through ports does not make a difference regarding the behavior.

interface my_interface;
    logic      some_byte;
endinterface
module fpga_tester(
    output  logic          test_byte
);
    //Create an interface instance
    my_interface test_interface();
    
    //Use the interface instance to bridge between two modules
    data_creator m_create(.test_interface);
    pass_through m_pass(.test_interface, .byte_out(test_byte));
endmodule
module data_creator(
    my_interface                test_interface
);
    initial test_interface.some_byte = 8'b1010_1010;
endmodule
module pass_through(
    my_interface                test_interface,
    output  logic          byte_out
);
    assign byte_out = test_interface.some_byte;
endmodule

The output pins still all end up grounded.

I keep including the initial statement in the code because that's what caused the problems in my real design. I tried adding an interface to simplify ports, and suddenly the synthesis results stopped matching simulation. It came down to Quartus ignoring all the initial statements for registers that were part of the interface. I needed everything to start with specific arbitrary values (which worked fine before adding the interface), but the inclusion of an interface forced all the registers inside it to always initialize to 0.