Problem with SV Interfaces in Quartus

Well, going back to the Quartus complaint about no source for the signal, your simplistic example probably just needs ANY driver, reset or otherwise. i.e. you don't need to add the fake reset, just the 'posedge clk' is enough.

See modified snippet below, which at least works the same in Modelsim and eliminates the Quartus warnings. Not sure if this is a better fit for your existing actual code base.

I'm not sure why the struct vs. interface is apparently receiving different treatment within Quartus; you may need to file a service request to find out.

Good luck.

interface my_interface;
    logic      some_byte;
    initial some_byte = 8'b1010_1010;
endinterface
module fpga_tester(
	input wire clk,
    output  logic          test_byte
);
    my_interface test_interface();
	
    always @(posedge clk)
	begin
		test_interface.some_byte = test_interface.some_byte + 1'b1;
	end
			
    assign test_byte = test_interface.some_byte;
endmodule