Problem with SV Interfaces in Quartus

In "Controlling the Power-Up State of Verilog HDL Designs," Altera says:

--- Quote Start ---

In Integrated Synthesis, the initial value corresponds to the power-up state of the object that models the variable in the synthesized design. For example, if a variable represents an inferred register, then the variable's initial value corresponds to the register's power-up level. By translating initial values into power-up conditions, Integrated Synthesis ensures that the behavior of the synthesized design matches the simulated behavior of your design as closely as possible.

Quartus II Integrated Synthesis honors initial values on variables and signals when possible. It honors initial values on I/O and combinational nets with no drivers. It also honors initial values on inferred registers and memories if your target device supports initialization of memories and registers. Integrated Synthesis does not honor initial values on inferred latches or combinational nets with actual drivers.

In Verilog, you can specify a variable's initial value in an initial construct or in the variable's declaration itself. For example, the following Verilog fragment uses an initial construct to assign an initial value to the variable enable:

reg enable;

initial begin

enable = 1'b1;

end

--- Quote End ---

I tried initial statements inside the interface declaration, but it did not help. No matter where I put the initial block, it gets ignored if it's dealing with anything in an interface. Initial blocks work in practice for standalone (not inside an interface) registers, ram, and structures in Quartus.

My real design has clocks in it, but unfortunately no resets. I'd rather not have to add reset networks to existing code just to be able to use interfaces. It's an interesting point about resets, though, since Quartus also takes power-up values from the reset condition coded for synchronous logic. For a goofy experiment, I rewrote my example above to add a completely unused clock and reset line to the design. Since the clock and reset values are hard coded, the clock will never toggle and the reset will never assert:

interface my_interface;
    logic      some_byte;
endinterface
module fpga_tester(
    output  logic          test_byte
);
    //Create an interface instance
    my_interface test_interface();
    
    //Use the interface instance to bridge between two modules
    data_creator m_create(.test_interface, .clk('0), .reset('0));
    pass_through m_pass(.test_interface, .byte_out(test_byte));
endmodule
module data_creator(
    my_interface                test_interface,
    input                       reset,
    input                       clk
);
    always @(posedge clk or posedge reset) begin
        if(reset)   test_interface.some_byte = 8'b1010_1010;    
    end
endmodule
module pass_through(
    my_interface                test_interface,
    output  logic          byte_out
);
    assign byte_out = test_interface.some_byte;
endmodule

Result: it recognizes the power-up condition!

So it looks like I can trick Quartus into working around what appears to be a bug if I just add a never-asserted reset to all the modules where I have initial blocks and want to use interfaces.