Problem with SV Interfaces in Quartus

I'm the same user writing from a different account. Thank you for putting time into this. It gets a little clearer to me with each new experiment. Your code worked for me, and it led me to realize that Quartus isn't necessarily confused by initial blocks with interfaces. The issue seems to be about the combination of initial blocks specifically with interfaces that don't synthesize into clocked logic. Going back to my first post example, ModelSim and Quartus match in behavior if one simple change is made:

interface my_interface;
    logic      some_byte;
endinterface
module fpga_test(
    input   wire                clk,
    output  logic          test_byte
);
    my_interface test_interface();
    
    assign test_byte = test_interface.some_byte;
    
    initial test_interface.some_byte = 8'b1010_1010;
    always @(posedge clk) test_interface.some_byte <= test_interface.some_byte + 1'd1; //Adding clocked logic here
endmodule

That seems to be starting with test_byte equal to 8'b1010_1010 across platforms. Note that the caveat of requiring clocked behavior was not necessary when using a struct. That makes this still seem like a bug, but I can see how it is an arguable corner case.

So the summary of the whole situation seems like this:

-I added interfaces to working code to simplify it.

-The code behavior no longer matched between ModelSim and Quartus.

-The difference appeared to be due to registers initializing differently after adding interfaces.

-I made a simple test case of an interface with an initial statement and found different behavior between ModelSim and Quartus.

-The test case was *too* simple, and as a result brought up a small bug in Quartus.

-I mistook the small bug for being the source of worse headaches than it actually is.

It also seems to be important to note that even with the clocked logic, if I move the initial block inside the interface then it does not work. ModelSim sees the initialization, but Quartus does not. Here's that version for reference:

interface my_interface;
    logic      some_byte;
    
    initial some_byte = 8'b1010_1010;
endinterface
module fpga_test(
    input   wire                clk,
    output  logic          test_byte
);
    my_interface test_interface();
    
    assign test_byte = test_interface.some_byte;
    
    always @(posedge clk) test_interface.some_byte <= test_interface.some_byte + 1'd1;
endmodule