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Altera_Forum's avatar
Altera_Forum
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12 years ago

Problem with SV Interfaces in Quartus

This will be a contrived example to illustrate a point. I'll start from an incredibly simple module design that does nothing but hold output pins in a constant pattern. module fpga_tester( ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

To Quartus' credit, it appears to be complaining about your code before removing the registers. 

Warning (12161): Node "my_interface:test_interface|my_interface.some_byte" is stuck at GND because node is in wire loop and does not have a source

i.e. maybe explore the problem with a slightly more complicated example closer to your actual problem you've run into?

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However, I'm trying to use this example to show a larger problem, which is that interfaces in Quartus don't seem to properly support registers.

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As-is, I think I would qualify the problem further as "Quartus doesn't seem to properly support initial statements for registers in interfaces that do not have any sources to drive them", which I'm guessing is not your actual problem in your actual project.