Parameterized verilog module instance name in verilog or system verilog

Question

Hi,

I am trying create verilog module that can support parameterized instance name. I understand that the signal width and other such things can be parameterized. But can we also parameterize the module instance name?

In following code, I am curious if there is any way somedynamicinstancename can be parameterized also? i can try to use system verilog if that can help here

Prompt response is greatly appreciated.

`timescale 1 ns/100 ps

module gmon # (

parameter WIDTH = 32

)

(Clk, Rst, SignalName);

// PCIE MST_BIF

input Clk;

input Rst;

input [WIDTH-1:0] SignalName;

// input [31:0] SignalName_ret

reg [WIDTH-1:0] SignalName_d1;

//reg [31:0] SignalName_d2;

always @ (posedge Clk) begin

SignalName_d1 <= SignalName;

// SignalName_d2 <= SignalName_ret;

end

wire b = some combinatroial log;

//assign RipLogChangeT1 = !Rst & (SignalName_d2 != SignalName_ret);

test_module# (.FIFOBUF_WIDTH(WIDTH)) somedynamicinstancename (

.reset(Rst), //CHECK THIS -- ACTIVE HIGH

.wclk(Clk),

.out_data_valid(b),

.out_data(SignalName[WIDTH-1:0]),

.out_eom(1'b0),

.out_flush_file(1'b0),

.out_flush_pipe(1'b0)

);

endmodule

altera_forum · Answer

You cannot manipulate identifier names (e.g. instance or variable names) as if they were strings to pass around in Verilog or SystemVerilog. You can use a text macro that will substitute any arbitrary text for you, but that is a compiler directive and not something you can parameterize on an instance by instance basis.

It might help if you could explain why you want to do this. There may be other alternatives.

altera_forum · Answer

As Dave_59 comments, if you could clarify what you are trying to do, we can help.

For example, the concept of "SomeDynamicInstanceName" is supported by configurations and/or dynamic binding. For example, if I had a counter implemented in Verilog, and I have a version for Altera and another version for Xilinx, eg., counter_altera.v and counter_xilinx.v, then I can write a compilation script that will compile just one of those files to create the instance used in the design. This is "dynamic" to some degree. The VHDL language supports configurations where you can map a component definition to a specific instance, eg., in the code you could use an instance of counter, but then use a binding to implement that counter using the Altera or Xilinx instance. Verilog and SystemVerilog likely have a similar feature, though I have not used it.

I posted an example for VHDL configurations in this thread a while ago (see Post#18)

http://www.alteraforum.com/forum/showthread.php?t=30414&page=2

Cheers,

Dave

altera_forum · Answer

--- Quote Start ---

You cannot manipulate identifier names (e.g. instance or variable names) as if they were strings to pass around in Verilog or SystemVerilog. You can use a text macro that will substitute any arbitrary text for you, but that is a compiler directive and not something you can parameterize on an instance by instance basis.

It might help if you could explain why you want to do this. There may be other alternatives.

--- Quote End ---

I would like to create a generic verilog module with parametrized width. In this verilog module, I have fifo of paramerized width that on the side is connected to c++ program. Thus it is a software transactor that we used to log transactioins stored in fifo in a text file for debug purpose. Someone else created c++ program but it derives the text file logger file name and the internal signal name from the fifo instance name. Thus if I can make the fifo instance name parameterized - just like the width then I can have generic text logger that I can use to support variable width signals.

altera_forum · Answer

Your explanation needs a little more work. The name of the Verilog module to your C++ code is completely immaterial. Assuming the FIFO is memory mapped, then all the C++ code needs is the address of the FIFO that it needs to read from. The C++ code does not care what the component name used in the HDL is. Sure, if you are writing the C++ to use an address map generated by Qsys, you need to look-up the name used in the Qsys system, but that name is specified in the Qsys GUI, not in the HDL implementation.

If you want to create a component that C++ code can identify, then you need a set of status registers that the C++ code can read from, eg., IP version, and HDL generics, such as the FIFO bit-width. The C++ code would read those registers first, and then go and read from the FIFO.

Perhaps I misunderstand though .... :)

Cheers,

Dave

altera_forum · Answer

--- Quote Start ---

Your explanation needs a little more work. The name of the Verilog module to your C++ code is completely immaterial. Assuming the FIFO is memory mapped, then all the C++ code needs is the address of the FIFO that it needs to read from. The C++ code does not care what the component name used in the HDL is. Sure, if you are writing the C++ to use an address map generated by Qsys, you need to look-up the name used in the Qsys system, but that name is specified in the Qsys GUI, not in the HDL implementation.

If you want to create a component that C++ code can identify, then you need a set of status registers that the C++ code can read from, eg., IP version, and HDL generics, such as the FIFO bit-width. The C++ code would read those registers first, and then go and read from the FIFO.

Perhaps I misunderstand though .... :)

Cheers,

Dave

--- Quote End ---

Hi,

I am sorry the details but unloading of FIFO may be verndor specific software which may create a packet containing the module instance name and transaction data if the fifo is not empty. This information may be parsed by c++ code to generate a log file. Thus I am under the impression that the address part is transparent. We have to add/remove so many such monitors that it is possible that addressing can change and hence the addressing information may have been abstracted out. Instead the module instance name may be passed. This is for a hardware emulation project. :)

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Parameterized verilog module instance name in verilog or system verilog

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