Parameterized verilog module instance name in verilog or system verilog

Your explanation needs a little more work. The name of the Verilog module to your C++ code is completely immaterial. Assuming the FIFO is memory mapped, then all the C++ code needs is the address of the FIFO that it needs to read from. The C++ code does not care what the component name used in the HDL is. Sure, if you are writing the C++ to use an address map generated by Qsys, you need to look-up the name used in the Qsys system, but that name is specified in the Qsys GUI, not in the HDL implementation.

If you want to create a component that C++ code can identify, then you need a set of status registers that the C++ code can read from, eg., IP version, and HDL generics, such as the FIFO bit-width. The C++ code would read those registers first, and then go and read from the FIFO.

Perhaps I misunderstand though .... :)

Cheers,

Dave