Parameterized verilog module instance name in verilog or system verilog

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I am sorry the details but unloading of FIFO may be verndor specific software which may create a packet containing the module instance name and transaction data if the fifo is not empty. This information may be parsed by c++ code to generate a log file. Thus I am under the impression that the address part is transparent. We have to add/remove so many such monitors that it is possible that addressing can change and hence the addressing information may have been abstracted out. Instead the module instance name may be passed. This is for a hardware emulation project. :)

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Hmm, I think maybe you need to draw a block diagram of your concept. As far as you original question goes it relates to HDL that once synthesized is "fixed". The only way software can determine any characteristics of the hardware will be by reading registers in the hardware or reading a hardware description (like the files Qsys generates).

I'm sure this all makes complete sense to you, but if you could create a block diagram ... and eventually make me understand, I'm sure others will too :)

Cheers,

Dave