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Altera_Forum
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10 years ago

Parameterized verilog module instance name in verilog or system verilog

Hi, I am trying create verilog module that can support parameterized instance name. I understand that the signal width and other such things can be parameterized. But can we also parameterize...
Altera_Forum's avatar
Altera_Forum
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10 years ago

You cannot manipulate identifier names (e.g. instance or variable names) as if they were strings to pass around in Verilog or SystemVerilog. You can use a text macro that will substitute any arbitrary text for you, but that is a compiler directive and not something you can parameterize on an instance by instance basis.

It might help if you could explain why you want to do this. There may be other alternatives.