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Your explanation needs a little more work. The name of the Verilog module to your C++ code is completely immaterial. Assuming the FIFO is memory mapped, then all the C++ code needs is the address of the FIFO that it needs to read from. The C++ code does not care what the component name used in the HDL is. Sure, if you are writing the C++ to use an address map generated by Qsys, you need to look-up the name used in the Qsys system, but that name is specified in the Qsys GUI, not in the HDL implementation.
If you want to create a component that C++ code can identify, then you need a set of status registers that the C++ code can read from, eg., IP version, and HDL generics, such as the FIFO bit-width. The C++ code would read those registers first, and then go and read from the FIFO.
Perhaps I misunderstand though .... :)
Cheers,
Dave
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Hi,
I am sorry the details but unloading of FIFO may be verndor specific software which may create a packet containing the module instance name and transaction data if the fifo is not empty. This information may be parsed by c++ code to generate a log file. Thus I am under the impression that the address part is transparent. We have to add/remove so many such monitors that it is possible that addressing can change and hence the addressing information may have been abstracted out. Instead the module instance name may be passed. This is for a hardware emulation project. :)
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