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You cannot manipulate identifier names (e.g. instance or variable names) as if they were strings to pass around in Verilog or SystemVerilog. You can use a text macro that will substitute any arbitrary text for you, but that is a compiler directive and not something you can parameterize on an instance by instance basis.
It might help if you could explain why you want to do this. There may be other alternatives.
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I would like to create a generic verilog module with parametrized width. In this verilog module, I have fifo of paramerized width that on the side is connected to c++ program. Thus it is a software transactor that we used to log transactioins stored in fifo in a text file for debug purpose. Someone else created c++ program but it derives the text file logger file name and the internal signal name from the fifo instance name. Thus if I can make the fifo instance name parameterized - just like the width then I can have generic text logger that I can use to support variable width signals.
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