Parameterized verilog module instance name in verilog or system verilog

As Dave_59 comments, if you could clarify what you are trying to do, we can help.

For example, the concept of "SomeDynamicInstanceName" is supported by configurations and/or dynamic binding. For example, if I had a counter implemented in Verilog, and I have a version for Altera and another version for Xilinx, eg., counter_altera.v and counter_xilinx.v, then I can write a compilation script that will compile just one of those files to create the instance used in the design. This is "dynamic" to some degree. The VHDL language supports configurations where you can map a component definition to a specific instance, eg., in the code you could use an instance of counter, but then use a binding to implement that counter using the Altera or Xilinx instance. Verilog and SystemVerilog likely have a similar feature, though I have not used it.

I posted an example for VHDL configurations in this thread a while ago (see Post#18)

http://www.alteraforum.com/forum/showthread.php?t=30414&page=2

Cheers,

Dave