New ContributorOn chip ADC hangs up in 10M50DAF256I76
We are using the part 10M50DAF256I76 in one of our designs. In this design we are using the available on chip modular dual ADC. The interface for the ADC is generated inside QSYS with the following settings as shown in the images below. The ADC IP is operating at 100 MHz and the ADC PLL is set to operate at 10MHz. We are using the tool Quartus Prime Version 18.1.0 SJ Standard edition to build our design.
With certain builds we find the on-chip ADC getting hanged on bootup. We did add STP to the signals present inside the ADC IP block and observed that FSM inside altera_adc_control for ADC1 after exiting the state PWRUP_CH (refer the image below) doesn’t enter any of the other states inside the FSM. It is also evident from the STP capture that sync ready and clk_dft_hl is high before the FSM exits PWRUP_CH so as per the logic mentioned in altera_modular_adc_control_fsm.v the FSM is supposed to transition to the state PWRUP_SOC. Another important point to note is that from the STP it is observed that while the FSM was in PWRUP_CH state, tsen input was high meaning the TSD channel of the ADC 1 is being sampled.
Requesting you to help us in debugging further as to why it is not entering the any of the FSM state after exiting PWRUP_CH and let us know why it appears only in certain Quartus build.
In-case the images are not clear, please refer to the word document attached with this post.
