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sagarsonavaneBH
New Contributor
New ContributorOn chip ADC hangs up in 10M50DAF256I76
We are using the part 10M50DAF256I76 in one of our designs. In this design we are using the available on chip modular dual ADC. The interface for the ADC is generated inside QSYS with the following ...
Ash_R_Altera
Regular Contributor
Regular ContributorWhat is the frequency of the clock port? Is the timing analysis clean, without any negative slack?
For the run bit, it is used to start the ADC conversion. For Single cycle mode, this bit should be set by the user to start the conversion. After conversion finishes for the last slot, the IP clears it. Refer Table 8 in the following link: Intel MAX 10 Analog to Digital Converter User Guide
sagarsonavaneBHWhat is the frequency of the clock port? ADC IP is operating at 100 MHz and the ADC PLL is set to operate at 10MHz.
Is the timing analysis clean, without any negative slack? NO, there are no timing error related to ADC IP or ADC Driver.
Like you said we are setting the ADC Command Register to 0x03 i.e.
Mode = Single cycle mode
Run Bit = true
