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sagarsonavaneBH's avatar
sagarsonavaneBH
Icon for New Contributor rankNew Contributor
5 years ago

On chip ADC hangs up in 10M50DAF256I76

We are using the part 10M50DAF256I76 in one of our designs. In this design we are using the available on chip modular dual ADC. The interface for the ADC is generated inside QSYS with the following ...
Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Sagar,

Looking at the waveform that you have shared, clk_dft signal frequency does not seems to be right. It should be 250KHz (4000 ns) which is your ADC sample rate in the IP wizard. From the waveform it definitely not near to that frequency.

Please check the freq of clk_dft in a working build.

Make sure that the clock to the ADC PLL i.e. 10 MHz is stable and has no noise.

Also monitor if the reset_sink_reset_n and adc_pll_locked_export to the IP are constantly set to high.


Regards