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MZorr1's avatar
MZorr1
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5 years ago

Old Verilog Library not recognized by Compiler

I have an old Verilog design which I am trying to compile into a MAX10M08. My problem is that the synthesis analysis doesn't recognize either the libraries I have specified for the project or doesn't recognize the library parts. I have made sure that the paths are correct. The original design is for a 65C02 which was made into an ASIC 25 years ago but, it should still work. I have selected Verilog 1995 as the HDL input. Attached is a small part of one of the libraries. It shows the first three modules, aa21, aa22 and aa31. There are hundreds of other modules like this in the library but none are recognized. Should there be a header a the top of the file, in order for Quartus II to recognize it as a library file? I have worked on this for a while. The error message I get is like this for all the parts:

Error (12006): Node instance "NA21_U248" instantiates undefined entity "na21". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.

The one node line of code which generated the error is this:

na21 NA21_U248 (.Q(N285),.A(N138),.B(N260))

The two libraries in the project are identical except that one has lower case na21 modules and the other has upper case NA21 modules.

Can anyone help me with this?

Thank You.

5 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Where are you putting the library file and how are you referencing the file? In Quartus, you need to point to where the file is located (if it's not in the project directory) from Tools -> Options -> IP Catalog Search Locations.

    In the code for your design, you should also have `include to point to the file.

    Have you tried these?

    #iwork4intel

  • MZorr1's avatar
    MZorr1
    Icon for New Contributor rankNew Contributor
    5 years ago

    Thank You for the response. I am using the Quartus Prime Lite Edition (Free). In checking the comparison chart between editions, it does says it supports Verilog design entry. Seems that it should work but, I don't really know if the library sample I provided in my post, has the correct module syntax/structure, to be recognized as a valid library.

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Yes it could be due to your addressing path maybe you can double check it.

  • MZorr1's avatar
    MZorr1
    Icon for New Contributor rankNew Contributor
    5 years ago

    Thank You for the responses. I do have the two libraries I need to use, in the project directory and also specified in the project libraries and in the IP library selections. The paths are correct.

    I don't have them in the "Include" statement at the top of the code for the design. Could you give me an example for the Include statement in the code? The two library names are "ASICUC.LIB" and "ASICLC.LIB".

    I appreciate your response.

    This is how the top of the project looks like:

    `timescale 1ns/10ps

    module TOPLEVEL (ADCZ,CMPZ,ICKPC,ICKSR0,ICKSR1,ICKSR6,ICKSR7,ICLKSTP,ICLRMH,

    ICNAU0,ICNAU1,ICNAU2,ICNAU3,ICNAU4,IDEN,IFETCH,INCEN,IRDACDO,

    IRDMDDO,IRDMHDO,IRDMLAL,IRDMLDO,IRDPCAL,IRDPHDO,IRDPLDO,IRDPSDO,