No signal changes when using VHDL testbench with ModelSim

I'm trying to write a VHDL testbench for ModelSim (switching from using the quartus 9.1 waveform editor)

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-- Set up this testbench as an entity
entity test_cpld is
end test_cpld;
-- Create an implementation of the entity
-- (May have several per entity)
architecture testbench of test_cpld is
  -- Set up the signals under test
  signal cart_present : std_logic := '1';
  signal t0 : std_logic := '0';
  begin
    -- dut = device under test (same name as top project from Quartus)
    dut : entity work.cpld
      -- Map the ports from the dut to this testbench
      port map (
        eff_cart_present => cart_present,
        timer_0 => t0,
        );
    -- Set up the signals
    stimulus : process is
      begin
        cart_present <= '0';
        loop
          t0 <= '0';
          wait for 100 ps;
          t0 <= '1';
          wait for 100 ps;
        end loop;
      end process stimulus;
end architecture testbench;