Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

No signal changes when using VHDL testbench with ModelSim

I'm trying to write a VHDL testbench for ModelSim (switching from using the quartus 9.1 waveform editor) I feel like this is a pretty simple procedure... everything compiles, no warnings, but w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Please read the warning messages from Modelsim - it says right there in your screen shot that the inout drivers for timer_0 and eff_cart_present are uninitialized, i.e., 'U'.

Cheers,

Dave