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Altera_Forum's avatar
Altera_Forum
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13 years ago

No signal changes when using VHDL testbench with ModelSim

I'm trying to write a VHDL testbench for ModelSim (switching from using the quartus 9.1 waveform editor) I feel like this is a pretty simple procedure... everything compiles, no warnings, but w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Try:

vsim -t ps test_cpld

and if it works, then as Tricky comments, the reason you see nothing is the default timescale.

Since your test does not really need a 100ps timescale, change it to 1ns or greater. That'll save having to remember to change the simulator timescale.

Cheers,

Dave