No signal changes when using VHDL testbench with ModelSim

Interesting note about the resolution!

I changed my clock width to 100us, and simulated out to 10ms, and the same response. Still just a flatline 'U' for both of my signals.

Is there something wrong with the way I'm running? I'm selecting both vhdl files (the module and my testbench) and choosing "Compile Selection..." (no errors) - or compiling them at the console using vcom filename.vhd - to run I'm either choosing "Start Simulation..." and bowsing the work library for the test_cpld architecture, or am doing the same with the 'vsim' command. No matter how I slice it, I don't get any data in my waveform viewer.