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Altera_Forum
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13 years ago

No signal changes when using VHDL testbench with ModelSim

I'm trying to write a VHDL testbench for ModelSim (switching from using the quartus 9.1 waveform editor) I feel like this is a pretty simple procedure... everything compiles, no warnings, but w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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Still just a flatline 'U' for both of my signals.

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Check that the timer_0 port is defined as an input port, otherwise you could have a driver conflict (though I think that would come up as an 'X').

Cheers,

Dave