My SOPC has cfi_flash,and its base address is 0x0.But when I used the Flash Programmer in Nios IDE, it paused with No CFI table found at address 0x00000000 Leaving target processor paused It could't find the cfi_flash? I checked in Nios commend shell,also the problem. what's the matter?

Hi, I had the same problem in a design that has SOPC and a cfi flash. In my case, the problem was VHDL coding. The design worked fine in Quartus 5.1 but not in Quartus 7.1 Exact same code. We later found out that Quartus 6.X and later implemented stricter VHDL synthesis standards than Quartus 5.1. When we put a logic analyser on the pins, it looked the same for flash accesses, but the Flash Programmer in Nios IDE always gave the same error you described if the design was compiled using 7.1. I dont remember the exact coding that was the issue as I dont have the file diff's in front of me but I seem to remember that it had something to do with an inout port. The data was going out the FPGA ok but the input side was not getting to a lower level instantiation. It was the flash data pins that were not getting to where they needed to go, and with the flash reponding properly on the logic analyzer, it made debug really frustrating. Altera FAE informed us of the change in how quartus interpreted VHDL between 5.1 and 6.X and we made a simple fix to the code that allowed programming using 6.X and later versions of quartus. I'm not saying this is the problem you have but it was the issue I had with the same messages you are seeing.

You can try the memory test to see if your flash controller is working properly or not.

What type of Flash device is it and how is it connected to your system (in terms of SOPC components, address and data pins etc.)? It sounds like something pretty fundamental to me. Have you tried the --debug option with the flash programmer to see what other information you can glean?

Here is an example of the code problem I inherited. --- Quote Start --- entity example is port ( flash_data : inout std_logic_vector(7 downto 0)); end entity example; architecture rtl of example is signal flash_data_internal : std_logic_vector(7 downto 0); begin --this works in quartus 5.1 but not 6.0 and above flash_data <= flash_data_internal; flash_inst: entity work.flash(rtl) port map ( flash_data => flash_data_internal --flash_data is inout in flash.vhd ); --this is the proper way flash_inst: entity work.flash(rtl) port map ( flash_data => flash_data --direct to the input port. ); --- Quote End --- The flash_data_internal signal allows the data to go out but provides no path for the data coming in.

Thank you , Thank you , Thank you, Thank you. 4 days trying to debug this problem, 4 days, and your post saved my A**. It works now. Thank you again. Do you know why signals defined as inout wouldn't work with intermediate signals like this ? Edited to add this is for : gmpstr

No CFI table found at address 0x00000000 | Altera Community

19 Replies

Altera_Forum
Honored Contributor
17 years ago
Hi, I had the same problem in a design that has SOPC and a cfi flash. In my case, the problem was VHDL coding. The design worked fine in Quartus 5.1 but not in Quartus 7.1

Exact same code. We later found out that Quartus 6.X and later implemented stricter VHDL synthesis standards than Quartus 5.1. When we put a logic analyser on the pins, it looked the same for flash accesses, but the Flash Programmer in Nios IDE always gave the same error you described if the design was compiled using 7.1. I dont remember the exact coding that was the issue as I dont have the file diff's in front of me but I seem to remember that it had something to do with an inout port. The data was going out the FPGA ok but the input side was not getting to a lower level instantiation. It was the flash data pins that were not getting to where they needed to go, and with the flash reponding properly on the logic analyzer, it made debug really frustrating. Altera FAE informed us of the change in how quartus interpreted VHDL between 5.1 and 6.X and we made a simple fix to the code that allowed programming using 6.X and later versions of quartus.

I'm not saying this is the problem you have but it was the issue I had with the same messages you are seeing.
Altera_Forum
Honored Contributor
17 years ago
You can try the memory test to see if your flash controller is working properly or not.
Altera_Forum
Honored Contributor
17 years ago
What type of Flash device is it and how is it connected to your system (in terms of SOPC components, address and data pins etc.)? It sounds like something pretty fundamental to me. Have you tried the --debug option with the flash programmer to see what other information you can glean?
Altera_Forum
Honored Contributor
17 years ago
Here is an example of the code problem I inherited.

--- Quote Start ---

entity example is
port
(
flash_data : inout std_logic_vector(7 downto 0));
end entity example;
architecture rtl of example is
signal flash_data_internal : std_logic_vector(7 downto 0);
begin

--this works in quartus 5.1 but not 6.0 and above
flash_data <= flash_data_internal;
flash_inst: entity work.flash(rtl)
port map
(
flash_data => flash_data_internal --flash_data is inout in flash.vhd
);

--this is the proper way
flash_inst: entity work.flash(rtl)
port map
(
flash_data => flash_data --direct to the input port.
);

--- Quote End ---

The flash_data_internal signal allows the data to go out but provides no path for the data coming in.
Altera_Forum
Honored Contributor
17 years ago
Thank you , Thank you , Thank you, Thank you. 4 days trying to debug this problem, 4 days, and your post saved my A**. It works now. Thank you again. Do you know why signals defined as inout wouldn't work with intermediate signals like this ?

Edited to add this is for : gmpstr
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
Thank you , Thank you , Thank you, Thank you. 4 days trying to debug this problem, 4 days, and your post saved my A**. It works now. Thank you again. Do you know why signals defined as inout wouldn't work with intermediate signals like this ?

Edited to add this is for : gmpstr
--- Quote End ---

I am facing this same issue
Info: Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Info: Resetting and pausing target processor: OK
Info: Reading System ID at address 0x111010B8: verified
Info: No CFI table found at address 0x10800000
Info: Leaving target processor paused
Error: Error code: 8 for command: nios2-flash-programmer "E:/Nios_Flash/sys1/software/gui_bsp/flash/gui_cfi_flash_0.flash" --base=0x10800000 --sidp=0x111010B8 --id=0x0 --timestamp=1368512084 --device=1 --instance=0 '--cable=USB-Blaster on localhost [USB-0]' --program

please explain me what you have done to fix this Bug ?

RD
asickrishna

Altera_Forum

Honored Contributor

12 years ago

@ gmpstr : interseting. Maybe the resolved type "std_logic_vector" is not good for inout. The unresolved "std_ulogic_vector" could be good

@asickrishna :

In a Nios II command Shell (see Windows start menu/programs/altera/... or "C:\altera\12.0sp1\nios2eds\Nios II Command Shell.bat" )

nios2-flash-programmer --debug --base=0x10800000

You will get something like this


 this is an example
Using cable "USB-Blaster ", device 1, instance 0x00
Resetting and pausing target processor: OK
Found CFI table in 16 bit mode
Raw CFI query table read from device:
   0: 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
  10: 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
  20: 51 00 52 00 59 00 02 00  00 00 40 00 00 00 00 00  Q.R.Y.....@.....
  30: 00 00 00 00 00 00 27 00  36 00 00 00 00 00 07 00  ......'.6.......
  40: 07 00 0A 00 00 00 03 00  05 00 04 00 00 00 17 00  ................
CFI query table read from device:
  10: 51 52 59 02 00 40 00 00  00 00 00 27 36 00 00 07  QRY..@.....'6...
  20: 07 0A 00 03 05 04 00 17  02 00 05 00 02 07 00 20  ...............
  30: 00 7E 00 00 01 00 00 00  00 00 00 00 00 00 00 00  .~..............
CFI extended table read from device:
   0: 50 52 49 31 33 08 02 01  01 04 00 00 01 B5 C5 02  PRI13...........
  10: 01 00 00 00 00 00 00 00  00 00 00 00 00 00 00 05  ................
  20: 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
  30: 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  ................
Read autoselect code 0001-227E (in 16 bit mode)
No CFI override data for 
Device size is 8MByte
Erase regions are:
  offset        0:   8 x 8K
  offset    10000: 127 x 64K
Device supports AMD style programming algorithm
Multi-byte programming with 32 byte buffer
Sector erase timeout is 16s
Word program timeout is 1ms
Buffer program timeout is 4ms

Altera_Forum
Honored Contributor
12 years ago
Hi

I got the CFI table in 16 bit mode.After getting CFI table also i got the error as Leaving Target processor paused.
Altera_Forum
Honored Contributor
12 years ago
It is not an error, just cycle power or reset the board.

You could use the -g option of nios2-flash-programmer.
Altera_Forum
Honored Contributor
12 years ago
I am getting error like this

Please find the attachment.
output.txt18 KB

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No CFI table found at address 0x00000000

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