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Altera_Forum
Honored Contributor
17 years agoHere is an example of the code problem I inherited.
--- Quote Start --- entity example is port ( flash_data : inout std_logic_vector(7 downto 0)); end entity example; architecture rtl of example is signal flash_data_internal : std_logic_vector(7 downto 0); begin --this works in quartus 5.1 but not 6.0 and above flash_data <= flash_data_internal; flash_inst: entity work.flash(rtl) port map ( flash_data => flash_data_internal --flash_data is inout in flash.vhd ); --this is the proper way flash_inst: entity work.flash(rtl) port map ( flash_data => flash_data --direct to the input port. ); --- Quote End --- The flash_data_internal signal allows the data to go out but provides no path for the data coming in.