Forum Discussion
Altera_Forum
Honored Contributor
17 years agoHi, I had the same problem in a design that has SOPC and a cfi flash. In my case, the problem was VHDL coding. The design worked fine in Quartus 5.1 but not in Quartus 7.1
Exact same code. We later found out that Quartus 6.X and later implemented stricter VHDL synthesis standards than Quartus 5.1. When we put a logic analyser on the pins, it looked the same for flash accesses, but the Flash Programmer in Nios IDE always gave the same error you described if the design was compiled using 7.1. I dont remember the exact coding that was the issue as I dont have the file diff's in front of me but I seem to remember that it had something to do with an inout port. The data was going out the FPGA ok but the input side was not getting to a lower level instantiation. It was the flash data pins that were not getting to where they needed to go, and with the flash reponding properly on the logic analyzer, it made debug really frustrating. Altera FAE informed us of the change in how quartus interpreted VHDL between 5.1 and 6.X and we made a simple fix to the code that allowed programming using 6.X and later versions of quartus. I'm not saying this is the problem you have but it was the issue I had with the same messages you are seeing.