Hi all, This is my first project in verilog, in Altera and in Cyclone 2 FPGA. I have many modules and when i try to connect the modules there are setup and hold problems occurred. Somehow by referring to quartus document i solved those by analysing in time quest timing analyzer. If i look at "Unconstrained paths Summary" in timing analyzer there are unconstrained clock, unconstrained input port, unconstrained input port path, unconstrained output port and unconstrained output port path. From the quartus document i came to know that these things can be solved by setting input delay and output delay, but i dont know how to calculate those delays because this is occuring when modules are interconnected. How can i solve this? Any help is appreciated. Thank you

Generally, you should know the board trace delay and the timing parameter of downstream/upstream device. You could give the detail description in TQ handbook and example in TQ cookbook. You could search these doc on altera web

Thank you for the reply. I will have a look at the document. Whether the method what i am following is right? am i in the right way?

--- Quote Start --- Thank you for the reply. I will have a look at the document. Whether the method what i am following is right? am i in the right way? --- Quote End --- Hi, be aware that the input delay and output delay only descripts the timing for the FPGA to the outside world. Timing violations between verilog modules will not be affected by this settings. If you have internal holdtime violations look to the clock generation. Do you have gated clocks or clocks generated by a ripple counter in your design ? Kind regards GPK

Excatly thats what i wanted to know, i wanted to know to how to overcome the timing violations between verilog modules. In the timing analyzer when i checked the report there are no holditme violations. Q> Do you have gated clocks or clocks generated by a ripple counter in your design ? A> Yes i have clocks generated by ripple counter. Most of the times i have used PLL megafunction, other times i cannot use PLL megafunction to generate clocks of lower frequency. So i have used counter to generate clock.

--- Quote Start --- Excatly thats what i wanted to know, i wanted to know to how to overcome the timing violations between verilog modules. In the timing analyzer when i checked the report there are no holditme violations. Q> Do you have gated clocks or clocks generated by a ripple counter in your design ? A> Yes i have clocks generated by ripple counter. --- Quote End --- Hi, with a ripple counter you add always a small delay to the next clock stage. If you have in your design paths between the different clock domains you will run into holdtime violation. Why not replace the ripple counter with a binary counter ? Kind regards GPK

Newbie question about SDC in Timing analyzer

14 Replies

Altera_Forum
Honored Contributor
15 years ago
Generally, you should know the board trace delay and the timing parameter of downstream/upstream device. You could give the detail description in TQ handbook and example in TQ cookbook. You could search these doc on altera web
Altera_Forum
Honored Contributor
15 years ago
Thank you for the reply. I will have a look at the document.
Whether the method what i am following is right? am i in the right way?
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
Thank you for the reply. I will have a look at the document.
Whether the method what i am following is right? am i in the right way?
--- Quote End ---

Hi,

be aware that the input delay and output delay only descripts the timing for the FPGA to the outside world. Timing violations between verilog modules will not be affected by this settings. If you have internal holdtime violations look to the clock generation. Do you have gated clocks or clocks generated by a ripple counter in your design ?

Kind regards

GPK
Altera_Forum
Honored Contributor
15 years ago
Excatly thats what i wanted to know, i wanted to know to how to overcome the timing violations between verilog modules. In the timing analyzer when i checked the report there are no holditme violations.

Q> Do you have gated clocks or clocks generated by a ripple counter in your design ?
A> Yes i have clocks generated by ripple counter. Most of the times i have used PLL megafunction, other times i cannot use PLL megafunction to generate clocks of lower frequency. So i have used counter to generate clock.
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
Excatly thats what i wanted to know, i wanted to know to how to overcome the timing violations between verilog modules. In the timing analyzer when i checked the report there are no holditme violations.

Q> Do you have gated clocks or clocks generated by a ripple counter in your design ?
A> Yes i have clocks generated by ripple counter.
--- Quote End ---

Hi,

with a ripple counter you add always a small delay to the next clock stage. If you have in your design paths between the different clock domains you will run into holdtime violation.
Why not replace the ripple counter with a binary counter ?

Kind regards

GPK
Altera_Forum
Honored Contributor
15 years ago
Thank you for the suggestions.
I have designed the clock using binary counter, but the result wont change.
By seeing this result is there any need to change the module design?:confused:
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
Thank you for the suggestions.
I have designed the clock using binary counter, but the result wont change.
By seeing this result is there any need to change the module design?:confused:
--- Quote End ---

Hi,

ok was a fast try. Can you post some of your timing violations here ?

Kind regards

GPK
Altera_Forum
Honored Contributor
15 years ago
I have attached the files, please have a look at those files.
multiple-attachments.zip218 KB
Altera_Forum
Honored Contributor
15 years ago
Hello,

from your second screenshot, you have several unconstrained clocks. That is, the analyzer knows they are clocks but has no ideia about their frequency and etc.

You need to constrain those clocks using create_clock or create_generated_clock properly.

BTW, take a look as this thread about gated and ripple clocks
http://www.alteraforum.com/forum/showthread.php?t=2388

The first screenshot also tells that you have several unconstrained I/O paths. This means that the analyzer has no idea about the external delays that affect these I/O signals.
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
Hello,

from your second screenshot, you have several unconstrained clocks. That is, the analyzer knows they are clocks but has no ideia about their frequency and etc.

You need to constrain those clocks using create_clock or create_generated_clock properly.

BTW, take a look as this thread about gated and ripple clocks
http://www.alteraforum.com/forum/showthread.php?t=2388

The first screenshot also tells that you have several unconstrained I/O paths. This means that the analyzer has no idea about the external delays that affect these I/O signals.
--- Quote End ---

Hi,

have look to this Altera paper :

http://www.altera.com/literature/manual/mnl_timequest_cookbook.pdf?gsa_pos=2&wt.oss_r=1&wt.oss=cookbook

There are a lot of info's about Timequest inside.

Kind regards

GPK

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Newbie question about SDC in Timing analyzer

14 Replies

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