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Altera_Forum
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15 years ago

Newbie question about SDC in Timing analyzer

Hi all, This is my first project in verilog, in Altera and in Cyclone 2 FPGA. I have many modules and when i try to connect the modules there are setup and hold problems occurred. Somehow b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Generally, you should know the board trace delay and the timing parameter of downstream/upstream device. You could give the detail description in TQ handbook and example in TQ cookbook. You could search these doc on altera web