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Altera_Forum
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15 years ago

Newbie question about SDC in Timing analyzer

Hi all, This is my first project in verilog, in Altera and in Cyclone 2 FPGA. I have many modules and when i try to connect the modules there are setup and hold problems occurred. Somehow b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Thank you for the suggestions.

I have designed the clock using binary counter, but the result wont change.

By seeing this result is there any need to change the module design?:confused:

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Hi,

ok was a fast try. Can you post some of your timing violations here ?

Kind regards

GPK