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Altera_Forum
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15 years ago

Newbie question about SDC in Timing analyzer

Hi all, This is my first project in verilog, in Altera and in Cyclone 2 FPGA. I have many modules and when i try to connect the modules there are setup and hold problems occurred. Somehow b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Thank you for the reply. I will have a look at the document.

Whether the method what i am following is right? am i in the right way?

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Hi,

be aware that the input delay and output delay only descripts the timing for the FPGA to the outside world. Timing violations between verilog modules will not be affected by this settings. If you have internal holdtime violations look to the clock generation. Do you have gated clocks or clocks generated by a ripple counter in your design ?

Kind regards

GPK