Newbie question about SDC in Timing analyzer

Excatly thats what i wanted to know, i wanted to know to how to overcome the timing violations between verilog modules. In the timing analyzer when i checked the report there are no holditme violations.

Q> Do you have gated clocks or clocks generated by a ripple counter in your design ?

A> Yes i have clocks generated by ripple counter. Most of the times i have used PLL megafunction, other times i cannot use PLL megafunction to generate clocks of lower frequency. So i have used counter to generate clock.