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Excatly thats what i wanted to know, i wanted to know to how to overcome the timing violations between verilog modules. In the timing analyzer when i checked the report there are no holditme violations.
Q> Do you have gated clocks or clocks generated by a ripple counter in your design ?
A> Yes i have clocks generated by ripple counter.
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Hi,
with a ripple counter you add always a small delay to the next clock stage. If you have in your design paths between the different clock domains you will run into holdtime violation.
Why not replace the ripple counter with a binary counter ?
Kind regards
GPK
Honored Contributor
