Need advice about coding style

I was going for a better answer but it took me 5 times to login successfully. This website is broken and ignored.

Ok. I conclude - just describe your intetion as algorithm then compiler will decide about implemantion. By the way, looking at code for full_adder_nbit is there upper limit for N when the logic sysnthesis with plus operator will be worst than using build-in PARALLEL_ADD structure , the last i found in IP-catalog. It is also about coding style - using built-in functions and blocks rather than reinventing one's own.

Let's go further.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
-- addition of two operands with carry-save
ENTITY full_adder_Nbit IS
GENERIC (
	N : POSITIVE := 4                     -- default operands size
);
PORT (
	clk : IN  STD_LOGIC;                  -- clock signal
	ci  : IN  STD_LOGIC;                  -- carry-in
	a   : IN  UNSIGNED (N-1 DOWNTO 0);    -- augend
	b   : IN  UNSIGNED (N-1 DOWNTO 0);    -- addend
	s   : OUT UNSIGNED (N-1 DOWNTO 0);    -- sum
	co  : OUT STD_LOGIC                   -- carry-out
);
END full_adder_Nbit;
ARCHITECTURE b OF full_adder_Nbit IS
	SIGNAL
		out_s  : UNSIGNED (N-1 DOWNTO 0);   -- new value for sum
	SIGNAL
		out_co : STD_LOGIC;                 -- new value for carry-out
BEGIN
-- provide outputs with recently calculated values (from p1)
	p0 : PROCESS (clk)
	BEGIN
		IF rising_edge(clk) THEN
			co <= out_co;
			s  <= out_s;
		END IF;
	END PROCESS p0;
-- calculate new values that will be outputed (for p0)
	p1 : PROCESS (ci, a, b)
	VARIABLE
		result_v : UNSIGNED (N DOWNTO 0);   -- intermediate result
	BEGIN
		result_v := ('0' & a) + ('0' & b) + ('0' & ci);
		out_co <= result_v(N);
		out_s  <= result_v(N-1 DOWNTO 0);
	END PROCESS p1;
END b;

Hi. Could anyone clarify me why i get multiplexor instead of register?

	function regCreate(
		signal clk : std_logic; aclr : std_logic; data : unsigned) return unsigned is
		variable temp : unsigned(data'range);
	begin
		if aclr = '1' then
			temp := to_unsigned(0, data'length);
		elsif rising_edge(clk) then
			temp := data;
		end if;
		return temp;
	end regCreate;

Will it be the same if I will use "procedure". Or should i shift down to component instance?

	function isRegZero(reg : unsigned) return std_logic is
		variable temp : std_logic;
	begin
		temp := '1';
		for i in reg'range loop
			temp := temp and (not reg(i));
		end loop;
		return temp;
	end isRegZero;

Why not stick to the coding guidelines and use processes?

Functions are not used for synchronous description because they have to be called from a sequential context (like a process). Functions also complete in 0 time and cannot have any time associated with them.

It seems that rising_edge evaluated at compile time in function.

	procedure regCreate(
		signal clk : IN std_logic; aclr : IN std_logic;
		data : IN unsigned; signal reg: OUT unsigned) is
	begin
		if aclr = '1' then
			reg <= to_unsigned(0, data'length);
		elsif rising_edge(clk) then
			reg <= data;
		end if;
	end regCreate;
	procedure regCreate(
		signal clk : IN std_logic; aclr, ce : IN std_logic;
		data : IN unsigned; signal reg: OUT unsigned) is
	begin
		if aclr = '1' then
			reg <= to_unsigned(0, data'length);
		elsif rising_edge(clk) then
			if ce = '1' then
				reg <= data;
			end if;
		end if;
	end regCreate;

library IEEE;
	use IEEE.std_logic_1164.all;
	use IEEE.numeric_std.all;
	use work.utility_pkg.all;
entity PulseGenerator is
	generic(
		REG_WIDTH : natural := 4
	);
	port(
		reset
		clk,	
		wrn,	
		wrk,	
		start : IN std_logic;
		data : IN unsigned(REG_WIDTH-1 downto 0);
		z : OUT std_logic
	);
end PulseGenerator;
architecture rtl1 of PulseGenerator is
	signal reg_N, reg_K : unsigned(data'range);
begin
		regCreate(wrn, reset, data, reg_N);
		regCreate(clk, reset, wrk, data, reg_K);
		z <= isRegZero(reg_N) and isRegZero(reg_K);
end rtl1;

thank you a lot of, Tricky. Your advices help me.