Need advice about coding style

Let's go further.

I see that built-in function has pipelining, I want to use it in my code, Im' confused a little bit. Any idea are welcome.

I wrote comments, is it good style for VHDL comments? What should be commented? The comments should be present in code for person who will be read it.

I remove initial values. I believe it is useful in simulation only, correct me if it is falsehood.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
-- addition of two operands with carry-save
ENTITY full_adder_Nbit IS
GENERIC (
	N : POSITIVE := 4                     -- default operands size
);
PORT (
	clk : IN  STD_LOGIC;                  -- clock signal
	ci  : IN  STD_LOGIC;                  -- carry-in
	a   : IN  UNSIGNED (N-1 DOWNTO 0);    -- augend
	b   : IN  UNSIGNED (N-1 DOWNTO 0);    -- addend
	s   : OUT UNSIGNED (N-1 DOWNTO 0);    -- sum
	co  : OUT STD_LOGIC                   -- carry-out
);
END full_adder_Nbit;
ARCHITECTURE b OF full_adder_Nbit IS
	SIGNAL
		out_s  : UNSIGNED (N-1 DOWNTO 0);   -- new value for sum
	SIGNAL
		out_co : STD_LOGIC;                 -- new value for carry-out
BEGIN
-- provide outputs with recently calculated values (from p1)
	p0 : PROCESS (clk)
	BEGIN
		IF rising_edge(clk) THEN
			co <= out_co;
			s  <= out_s;
		END IF;
	END PROCESS p0;
-- calculate new values that will be outputed (for p0)
	p1 : PROCESS (ci, a, b)
	VARIABLE
		result_v : UNSIGNED (N DOWNTO 0);   -- intermediate result
	BEGIN
		result_v := ('0' & a) + ('0' & b) + ('0' & ci);
		out_co <= result_v(N);
		out_s  <= result_v(N-1 DOWNTO 0);
	END PROCESS p1;
END b;