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Altera_Forum's avatar
Altera_Forum
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11 years ago

Need advice about coding style

Hello I'm Alex and I am novice for VHDL coding. if my english awful pls forgive me. I trying to understand VHDL PROCESS statement. I try with 1bit full adder with carry save function in Quartus2 v...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi. Could anyone clarify me why i get multiplexor instead of register? 

	function regCreate(
		signal clk : std_logic; aclr : std_logic; data : unsigned) return unsigned is
		variable temp : unsigned(data'range);
	begin
		if aclr = '1' then
			temp := to_unsigned(0, data'length);
		elsif rising_edge(clk) then
			temp := data;
		end if;
		return temp;
	end regCreate;