Need advice about coding style

It seems that rising_edge evaluated at compile time in function.

	procedure regCreate(
		signal clk : IN std_logic; aclr : IN std_logic;
		data : IN unsigned; signal reg: OUT unsigned) is
	begin
		if aclr = '1' then
			reg <= to_unsigned(0, data'length);
		elsif rising_edge(clk) then
			reg <= data;
		end if;
	end regCreate;
	procedure regCreate(
		signal clk : IN std_logic; aclr, ce : IN std_logic;
		data : IN unsigned; signal reg: OUT unsigned) is
	begin
		if aclr = '1' then
			reg <= to_unsigned(0, data'length);
		elsif rising_edge(clk) then
			if ce = '1' then
				reg <= data;
			end if;
		end if;
	end regCreate;

library IEEE;
	use IEEE.std_logic_1164.all;
	use IEEE.numeric_std.all;
	use work.utility_pkg.all;
entity PulseGenerator is
	generic(
		REG_WIDTH : natural := 4
	);
	port(
		reset
		clk,	
		wrn,	
		wrk,	
		start : IN std_logic;
		data : IN unsigned(REG_WIDTH-1 downto 0);
		z : OUT std_logic
	);
end PulseGenerator;
architecture rtl1 of PulseGenerator is
	signal reg_N, reg_K : unsigned(data'range);
begin
		regCreate(wrn, reset, data, reg_N);
		regCreate(clk, reset, wrk, data, reg_K);
		z <= isRegZero(reg_N) and isRegZero(reg_K);
end rtl1;