I was going for a better answer but it took me 5 times to login successfully. This website is broken and ignored.
Your statement can't be generalised. but one thing sure can; do not generate clock from logic, never so as a beginner.
state machine is just a methodology of design, old but could be useful to clear a disturbed mind. It is not essential and is just based on renaming of state on some registers outputs (state coding). I very rarely used state machine and when I do I use single process approach and don't want to know what is mealy or Moore who incidentally I believe were two PhD students having a drink at a pub then came with the idea. The difference between them is one clock delay between I think outputs of state machine and state transition.
In short, what you want to do at algorithm level decides what you should do at implementation level.