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Altera_Forum
Honored Contributor
11 years agoNeed advice about coding style
Hello I'm Alex and I am novice for VHDL coding. if my english awful pls forgive me. I trying to understand VHDL PROCESS statement. I try with 1bit full adder with carry save function in Quartus2 v...
Altera_Forum
Honored Contributor
11 years agoWill it be the same if I will use "procedure". Or should i shift down to component instance?
Before I believe that semantics of sequential operators the same as in "process". Perhaps i misunderstand "using function to generate schematic". I belive that fucntion do computation and generate some combinatorial schematic, why it can not manage with synchronous? function isRegZero(reg : unsigned) return std_logic is
variable temp : std_logic;
begin
temp := '1';
for i in reg'range loop
temp := temp and (not reg(i));
end loop;
return temp;
end isRegZero; with this function we get simple and-gate in schematic rather than big comparator