NativeLink fails to honor SystemVerilog request with Synplify Pro project

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I'm starting my first Altera project, and I'm having problems getting the NativeLink interface to properly initiate synthesis using Synplify Pro. I've set the HDL to SystemVerilog 2005 (in Settings->Verilog HDL Input), but when Synplify Pro runs it returns errors indicating it is not happy with the SV syntax. I don't see anywhere else within Quartus to set 'advanced' options which get passed to Synplify Pro to control it's operation. Do I have to run the synthesis separately from Quartus and rely on manual Tcl script execution to bring the results into Quartus and make this work?

Can anyone help?

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Hi nicolm,

I think it is the other way round. You have to set the SV switch in SynplifyPro, because Quartus uses the output of SyplifyPro ( its is a verilog netlist with the extension vqm). The synthesis part is done by SynplifyPro. In Quatus you have to set under EDA tool settings :

Desgin Entry/Synthesis -> SynplifyPro

When you start Quartus out of SynplifyPro the setting is done automatically.

Kind regards

GPK

I can run with no errors if I run Synplify Pro independantly, there is no problem here. The functionality I'm trying to get is to have Synplify Pro launched from Quartus using NativeLink. When I attempt this, Quartus doesn't set the appropriate settings to allow SV extensions and syntax. It also seems to ignore settings set in the prj file when I manually edit in what I want, and overwrites the prj file with it's incorrect settings.

Thanks

-mark

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I can run with no errors if I run Synplify Pro independantly, there is no problem here. The functionality I'm trying to get is to have Synplify Pro launched from Quartus using NativeLink. When I attempt this, Quartus doesn't set the appropriate settings to allow SV extensions and syntax. It also seems to ignore settings set in the prj file when I manually edit in what I want, and overwrites the prj file with it's incorrect settings.

Thanks

-mark

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Hi,

I tried it the other way round. Quartus also ignores the SV setting in SynplifyPro. But why will set in Quartus the option to SV ? In my point of view it should be done in SynplfyPro,

because it is used as synthesis tool. If it is set in SynplifyPro it should stay in the project file.

Kind regards

GPK

I don't know about Synplify Pro, but I had similar problems with NativeLink and ModelSim. IMHO, NativeLink is broken in many ways.

My solution was to use the ".SV" extension in the filename. Files with the SV extension are automatically assumed to be SystemVerilog by ModelSim. May be this would work with Synplify Pro as well.

pletz: According to him, NativeLink is overriding the Synplify Pro configuration by overwriting the Synplify Pro configuration file. That was exactly the same issue I had with ModelSim.

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I don't know about Synplify Pro, but I had similar problems with NativeLink and ModelSim. IMHO, NativeLink is broken in many ways.

My solution was to use the ".SV" extension in the filename. Files with the SV extension are automatically assumed to be SystemVerilog by ModelSim. May be this would work with Synplify Pro as well.

pletz: According to him, NativeLink is overriding the Synplify Pro configuration by overwriting the Synplify Pro configuration file. That was exactly the same issue I had with ModelSim.

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Hi,

I played a little bit with the "native-if" of SynplifyPro and Quartus. Both IF do not pass all constraints to the other tool. In my point of view they are not useable.

Kind regards

GPK