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I'm starting my first Altera project, and I'm having problems getting the NativeLink interface to properly initiate synthesis using Synplify Pro. I've set the HDL to SystemVerilog 2005 (in Settings->Verilog HDL Input), but when Synplify Pro runs it returns errors indicating it is not happy with the SV syntax. I don't see anywhere else within Quartus to set 'advanced' options which get passed to Synplify Pro to control it's operation. Do I have to run the synthesis separately from Quartus and rely on manual Tcl script execution to bring the results into Quartus and make this work?
Can anyone help?
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Hi nicolm,
I think it is the other way round. You have to set the SV switch in SynplifyPro, because Quartus uses the output of SyplifyPro ( its is a verilog netlist with the extension vqm). The synthesis part is done by SynplifyPro. In Quatus you have to set under EDA tool settings :
Desgin Entry/Synthesis -> SynplifyPro
When you start Quartus out of SynplifyPro the setting is done automatically.
Kind regards
GPK
Honored Contributor
