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Altera_Forum
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16 years ago

NativeLink fails to honor SystemVerilog request with Synplify Pro project

I'm starting my first Altera project, and I'm having problems getting the NativeLink interface to properly initiate synthesis using Synplify Pro. I've set the HDL to SystemVerilog 2005 (in Settings->...
Altera_Forum's avatar
Altera_Forum
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16 years ago

I don't know about Synplify Pro, but I had similar problems with NativeLink and ModelSim. IMHO, NativeLink is broken in many ways.

My solution was to use the ".SV" extension in the filename. Files with the SV extension are automatically assumed to be SystemVerilog by ModelSim. May be this would work with Synplify Pro as well.

pletz: According to him, NativeLink is overriding the Synplify Pro configuration by overwriting the Synplify Pro configuration file. That was exactly the same issue I had with ModelSim.