Mux INOUT port in VHDL

the brick: thanks for this clarification. I used to_x01 to solve problems when comparing states in the module reading SDA. If I just read 'H' on the line, a compare with '1' fails. According to my techbench I'm also reading 'H's into my internal sift register. I need to compare that later with a preassigned address (a std_logic_vector containing '0' and '1') which also always fails. Whats your suggested method to solve that?

Pauliman. Yes you can read inout ports. Just read it when you're driving 'Z' onto it. I assume you have a CS or WE port coming in, so you know when data is avaibable on the bus. If you dont - you wont know when to read it.

As I wrote in my initial post, I'm feeding the INOUT pins into a vector and then down into the EDIDOutput module where I'm trying to mux one to my I2C Master. The master has dedicated input and output signals which I'm trying to combine into the selected INOUT signal by the mux code I posted. Due to the nature of I2C all members can only pull-down the bus. I accomplished this by writing either '0' or 'Z' to SDA. But the problem is, that I don't understand why Quartus does not let me read SDA. The reading of SDA generates the error messages I posted.

I also don't understand why you can't compile the code. I guess, the problem isn't in the shown part. For clarfication my test application that did compile.

library ieee;
use ieee.std_logic_1164.all;
entity test0 is
  port 
  (
    sel : in integer range 0 to 3;
    sda : inout std_logic_vector(0 to 3);
    i_sda_o : in std_logic;
    i_sda_i : out std_logic
  );
end entity;
architecture rtl of test0 is
begin
mux_sda: process (sel, i_sda_o, sda)
begin
    sda <= (others => 'Z');
    if i_sda_o = '0' then
        sda(sel) <= '0';
    end if;
end process;
i_sda_i <= to_x01(sda(sel));
end rtl;

FvM: thanks for sharing your code.

signal sda_vec : std_logic_vector(1 to 2);
sda_vec(0) <= SDA1;
sda_vec(1) <= SDA2;

signal sda_vec_in, sda_vec_out : std_logic_vector(1 to 2);
sda_vec_in(1) <= SDA1;
sda_vec_in(2) <= SDA2;
SDA1 <= sda_vec_out(1);
SDA2 <= sda_vec_out(2);

I'm don't exactly understand what your original code was. Also in the assignment

SDA1 and SDA2 are the INOUT pins on the FPGA. The I2C master module is driving SDA either '0' or 'Z' and constantly read it.

entity FPGA is
    port (
        signal SDA1    : inout std_logic;
        signal SDA2    : inout std_logic
    );
end entity FPGA;
architecture rtl of FPGA is
    signal sda_vec : std_logic_vector(1 to 2);
begin
    sda_vec <= SDA1 & SDA2;
        
    MUX: entity work.MUX
        PORT MAP (
            sda => sda_vec,
        );
end rtl;
ENTITY MUX IS
    PORT (
        sda : inout std_logic_vector(1 to 2) := (others => 'Z');
    );
END MUX;
ARCHITECTURE rtl OF MUX is
    signal i_sda_i, i_sda_o : std_logic; -- input/output sda to/from I2C master
begin
    mux_sda: process (sel, sda) 
    begin     
        sda <= (others => 'Z');     
        if i_sda_o = '0' then
            sda(sel) <= '0';     
        end if; 
    end process; 
    i_sda_i <= to_x01(sda(sel));
end rtl;

There's no bidrectional assignment between SDA1 & SDA2 and port sda of entity MUX, just an unidirectional read:

sda_vec <= SDA1 & SDA2;
    MUX: entity work.MUX
        PORT MAP (
            sda => sda_vec,

So how can I connect SDA1 and SDA2 bidirectional to MUX? Separate ports for IN and OUT is what I now have.