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Tricky: does that mean that I'm not allowed to connect INOUT ports to internal modules and use them there are tri-state? I've grouped my tri-state pins (O?_DDCSDA) into a std_logic_vector (sda) and connected that vector to my EDIDOutput module in which the mux is located. Do I need to move the mux to the main module to get it working?
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Theres no problem with reading inout ports. The usual thing is the have them as inout only at the FPGA pin, and then convert it to separate in and out. With the incoming CS and WE inputs you should know when to read the port.
Honored Contributor
