Mux INOUT port in VHDL

I also don't understand why you can't compile the code. I guess, the problem isn't in the shown part. For clarfication my test application that did compile.

library ieee;
use ieee.std_logic_1164.all;
entity test0 is
  port 
  (
    sel : in integer range 0 to 3;
    sda : inout std_logic_vector(0 to 3);
    i_sda_o : in std_logic;
    i_sda_i : out std_logic
  );
end entity;
architecture rtl of test0 is
begin
mux_sda: process (sel, i_sda_o, sda)
begin
    sda <= (others => 'Z');
    if i_sda_o = '0' then
        sda(sel) <= '0';
    end if;
end process;
i_sda_i <= to_x01(sda(sel));
end rtl;