Mux INOUT port in VHDL

SDA1 and SDA2 are the INOUT pins on the FPGA. The I2C master module is driving SDA either '0' or 'Z' and constantly read it.

As I only need to communication with one of the two SDA pins at a time, I created the MUX of the initial post which is located in a lower module. This lower module has its sda input/outputs as a INOUT std_logic_vector. In the top level module, I combined the SDA1 and SDA2 pin into a signal of type std_logic_vector using the code I posted last. So the FPGA pins are combined into a vector and then connected to a INOUT port of the module where the MUX is in. The MUX is then either driving sda '0' or 'Z' and constantly reading it. And that seems to be the problem: driving and reading at the same time in the lower module does not synthesise for me.

The following is my initial code between FPGA-Pins and MUX, which does not synthesise.

entity FPGA is
    port (
        signal SDA1    : inout std_logic;
        signal SDA2    : inout std_logic
    );
end entity FPGA;
architecture rtl of FPGA is
    signal sda_vec : std_logic_vector(1 to 2);
begin
    sda_vec <= SDA1 & SDA2;
        
    MUX: entity work.MUX
        PORT MAP (
            sda => sda_vec,
        );
end rtl;
ENTITY MUX IS
    PORT (
        sda : inout std_logic_vector(1 to 2) := (others => 'Z');
    );
END MUX;
ARCHITECTURE rtl OF MUX is
    signal i_sda_i, i_sda_o : std_logic; -- input/output sda to/from I2C master
begin
    mux_sda: process (sel, sda) 
    begin     
        sda <= (others => 'Z');     
        if i_sda_o = '0' then
            sda(sel) <= '0';     
        end if; 
    end process; 
    i_sda_i <= to_x01(sda(sel));
end rtl;

Today I change the interface of MUX to separate IN and OUT ports and combined them to the physical pins in the top level module. That synthesises. But why?