Mux INOUT port in VHDL

FvM: thanks for sharing your code.

For further evaluation I modified the module where the MUX is in such, that it has separate IN and OUT ports for sda. In the top level module I combine this signals to the actual INOUT port pin. Interestingly that works. Can anyone explain me why?

Previously I had

signal sda_vec : std_logic_vector(1 to 2);
sda_vec(0) <= SDA1;
sda_vec(1) <= SDA2;

so that sda_vec consisted of INOUT elements. sda_vec was connected to the module, where the MUX is in and the MUX had to handle the tri-state logic.

Now I've changed it to

signal sda_vec_in, sda_vec_out : std_logic_vector(1 to 2);
sda_vec_in(1) <= SDA1;
sda_vec_in(2) <= SDA2;
SDA1 <= sda_vec_out(1);
SDA2 <= sda_vec_out(2);

and connected separate IN and OUT signals to the MUX, which does not have to care about tri-state anymore.

I also noticed, that Quartus is completely happy, if sda_vec_out contains 'Z'. The result seems not to change if I replace "SDA1 <= sda_vec_out(1);" by "SDA1 <= '0' when sda_vec_out(1) = '0' else 'Z';". What are the pro's and con's?