Not exactly. You've commented out the init_file and the defaults for altsyncram differ from what you want.
It's helpful to go to the Altera libs and see what they are doing. On my machine, altsyncram is in:
"
C:\intelFPGA\16.1\quartus\libraries\vhdl\altera_mf\altera_mf_components.vhd"
If using a wrapper such as the wizard generates, you just want to make the init_file a variable you can set. See lines that say "LOOK HERE".
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY ram_test IS
-- LOOK HERE add the following generic.
GENERIC (
my_init_file : string := "UNUSED"
)
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
);
END ram_test;
ARCHITECTURE SYN OF ram_test IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (12 DOWNTO 0);
BEGIN
q <= sub_wire0(12 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => my_init_file, -- LOOK HERE my_init_file passed in from ram_test instantiation in your main code.
intended_device_family => "MAX 10",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 8,
width_a => 13,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
So you can use the megawizard to generate a "template" but then "unwrap" it as kaz says and make things variables that the wizard hardwires.
Then when you instantiate ram_test (in my example), pass in the desired mif file name for each of the 128 cpu's in the generic map of each instance. If you use a simple pattern (eg file_001.mif, file_002.mif ...) you should be able to do it in a generate loop with dynamically generated file names. If you have not used VHDL generate, you should research that a bit on your own.
Some people would prefer to get rid of the ram_test wrapper altogether and just instantiate the altsyncram directly in their main code. Again, using your 128 different file name for init_file. That may be what you were suggesting. Just take the altsyncram instantiation generated by the wizard but make init_file a variable that you set in a generate loop. In your example:
CPU_LIST for i in 1 to 128 generate
CPU_RAM_I : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
init_file => GetInitFileName(i), -- LOOK HERE write function to generate file name for cpu 'i'
intended_device_family => "Stratix V",
lpm_type => "altsyncram",
numwords_a => 128,
numwords_b => 128,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK0",
power_up_uninitialized => "FALSE",
ram_block_type => "M20K",
read_during_write_mode_mixed_ports => "DONT_CARE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 7,
widthad_b => 7,
width_a => 32,
width_b => 32,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
address_a => address_a,
address_b => address_b,
clock0 => clock,
data_a => data_a,
data_b => data_b,
rden_a => rden_a,
rden_b => rden_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => sub_wire0,
q_b => sub_wire1
);
end generate;
I have not actually compiled the above code, so don't hold me to minor syntax errors.
I think this implicitly answers question 2; one entity and one architecture and a generic to load the correct data file. I've actually never used multiple architectures.
However, I doubt this whole approach is a good idea. I assume your cpu's have registers that need initialized along with RAM that needs a program loaded. The usual way to do this is to have a First Stage Boot Loader (FSBL) that goes and reads init data from a fixed address in user FLASH and then passes off to a second stage boot loader to load user programs (you may not need that). The bootstrap boot loader is in hardware in the CPU but you could probably share a single one across all the CPU's.
Of course, the mif files are strored in FLASH, but they will be part of your configuration stream. So every time you change the CPU firmware, you're going to have to resynthesize your whole system instead of just updating a user area of FLASH. This will make development especially cumbersome not to mention future upgrades.
I guess I'm the king of unsolicited suggestions this week. Only you know your system requirements.
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