Multiple RAM with different mif file

Thank you for your help!

I am not sure if I understand this fully. Correct me if I am wrong.

Suppose these 128 RAMs are all true dual port RAM. Then the set up for a True Dual Port RAM in altsyncram will be something look like following

altsyncram_component : altsyncram
   GENERIC MAP (
      address_reg_b => "CLOCK0",
      clock_enable_input_a => "BYPASS",
      clock_enable_input_b => "BYPASS",
      clock_enable_output_a => "BYPASS",
      clock_enable_output_b => "BYPASS",
      indata_reg_b => "CLOCK0",
     -- init_file => "init_data_1.mif",     -- this line state the initial file of the ram
      intended_device_family => "Stratix V",
      lpm_type => "altsyncram", 
      numwords_a => 128,
      numwords_b => 128,
      operation_mode => "BIDIR_DUAL_PORT",
      outdata_aclr_a => "NONE",
      outdata_aclr_b => "NONE",
      outdata_reg_a => "CLOCK0",
      outdata_reg_b => "CLOCK0",
      power_up_uninitialized => "FALSE",
      ram_block_type => "M20K",
      read_during_write_mode_mixed_ports => "DONT_CARE",
      read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
      read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
      widthad_a => 7,
      widthad_b => 7,
      width_a => 32,
      width_b => 32,
      width_byteena_a => 1,
      width_byteena_b => 1,
      wrcontrol_wraddress_reg_b => "CLOCK0"
   )
   PORT MAP (
      address_a => address_a,
      address_b => address_b,
      clock0 => clock,
      data_a => data_a,
      data_b => data_b,
      rden_a => rden_a,
      rden_b => rden_b,
      wren_a => wren_a,
      wren_b => wren_b,
      q_a => sub_wire0,
      q_b => sub_wire1
   );

If I want to make these map each ram to it I need to do something like

RAM_1 : altsyncram 
   GENERIC MAP (
       init_file => "init_data_1.mif"
   )
   PORT MAP (
   -- ports mapping
   ......
   );

Is that what you mean?

And I am not sure how to use loop to finish this. Since in my design, the top level module will be 128 processor connected together, and the RAM is located in each processor module. (Which I think is the lower level module).

And this leads to my Question 2 in the main post. Since each processor is the identical but the initial data of the ram, what is the better way to make it? One entity with multiple architectures?

Thanks again for your help.