When simulating a ROM component within the testbench file (for generating a data packet) I get the Modelsim warning # ** Warning: (vsim-3473) Component instance "inst_altera_testbench_packet_rom : altera_testbench_packet_rom" is not bound.The ROM is a 128 x 8 with a .hex file.The instantiation is all correct.Any idea what is wrong?Does Modelsim simulate ROM with Hex files?

I tried a .mif file but same issue.

More info:I fixed the "is not bound" fault by ensuring Modelsim compiled the ROM first by using a script.The next issue was 'unresolved defparam'So I added 'altera_mf_ver' library to the vsim script as community solution suggested.That fixed that one.But I am left with below - same for whether I use a hex or a mif file.# ** Warning: (vsim-3534) [FOFIR] - Failed to open file "./ip/altera_testbench_packet_rom/altera_testbench_packet.mif" for reading.# No such file or directory. (errno = ENOENT) : /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(263)# Time: 0 ps Iteration: 0 Instance: /testbench/inst_altera_testbench_packet_rom/altsyncram_component/m_default/altsyncram_inst# ERROR: cannot read ./ip/altera_testbench_packet_rom/altera_testbench_packet.mif.# ** Warning: (vsim-7) Failed to open readmem file "./ip/altera_testbench_packet_rom/altera_testbench_packet.ver" in read mode.# No such file or directory. (errno = ENOENT) : /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(48976)Its looking in entirely the wrong place for altera_mf.v and moreover, there is no such file as altera_testbench_packet.ver, if anything its altera_testbench_packet.v

I get it ,altera_testbench_packet.ver is supposed to be created from the .mif file by altera_mf.v.I changed my script to the attachment and now I get:# No such file or directory. (errno = ENOENT) : C:/intelFPGA_lite/18.1/quartus/eda/sim_lib/altera_mf.v(264)# Time: 0 ps Iteration: 0 Instance: /testbench/inst_altera_testbench_packet_rom/altsyncram_component/m_default/altsyncram_inst# ERROR: cannot read ./ip/altera_testbench_packet_rom/altera_testbench_packet.mif.# ** Warning: (vsim-7) Failed to open readmem file "./ip/altera_testbench_packet_rom/altera_testbench_packet.ver" in read mode.# No such file or directory. (errno = ENOENT) : C:/intelFPGA_lite/18.1/quartus/eda/sim_lib/altera_mf.v(48977)..The key has to be No such file or directory. (errno = ENOENT) : C:/intelFPGA_lite/18.1/quartus/eda/sim_lib/altera_mf.v(264) - but there is!!!

Hi,I try the ROM-1 Port IP on both hex and mif files without any problem. Check the attached design file and screenshot inside. May be try with that attached design file and see got any problem or not?Thanks,Best Regards,Sheng

Yours works even with Quartus 18.1 which is what I am using.The difference has to be I have a VHDL project and my ROM is part of the testbench file.I have to use a tcl script file to persuade Modelsim to compile the ROM first because of that.(tb.tcl)The issue has to be the vsim command or the fact I am using a MAX10.I attach my project.

Modelsim Lite Quartus 18.1 - simulating ROM

11 Replies

NGord
Occasional Contributor
2 years ago
I tried a .mif file but same issue.
- NGord
  Occasional Contributor
  2 years ago
  More info:
  I fixed the "is not bound" fault by ensuring Modelsim compiled the ROM first by using a script.
  The next issue was 'unresolved defparam'
  So I added 'altera_mf_ver' library to the vsim script as community solution suggested.
  
  That fixed that one.
  
  But I am left with below - same for whether I use a hex or a mif file.
  
  # ** Warning: (vsim-3534) [FOFIR] - Failed to open file "./ip/altera_testbench_packet_rom/altera_testbench_packet.mif" for reading.
  # No such file or directory. (errno = ENOENT) : /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(263)
  # Time: 0 ps Iteration: 0 Instance: /testbench/inst_altera_testbench_packet_rom/altsyncram_component/m_default/altsyncram_inst
  # ERROR: cannot read ./ip/altera_testbench_packet_rom/altera_testbench_packet.mif.
  # ** Warning: (vsim-7) Failed to open readmem file "./ip/altera_testbench_packet_rom/altera_testbench_packet.ver" in read mode.
  # No such file or directory. (errno = ENOENT) : /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v(48976)
  
  Its looking in entirely the wrong place for altera_mf.v and moreover, there is no such file as altera_testbench_packet.ver, if anything its altera_testbench_packet.v
  - NGord
    Occasional Contributor
    2 years ago
    I get it ,altera_testbench_packet.ver is supposed to be created from the .mif file by altera_mf.v.
    I changed my script to the attachment and now I get:
    
    # No such file or directory. (errno = ENOENT) : C:/intelFPGA_lite/18.1/quartus/eda/sim_lib/altera_mf.v(264)
    # Time: 0 ps Iteration: 0 Instance: /testbench/inst_altera_testbench_packet_rom/altsyncram_component/m_default/altsyncram_inst
    # ERROR: cannot read ./ip/altera_testbench_packet_rom/altera_testbench_packet.mif.
    # ** Warning: (vsim-7) Failed to open readmem file "./ip/altera_testbench_packet_rom/altera_testbench_packet.ver" in read mode.
    # No such file or directory. (errno = ENOENT) : C:/intelFPGA_lite/18.1/quartus/eda/sim_lib/altera_mf.v(48977)..
    
    The key has to be
    No such file or directory. (errno = ENOENT) : C:/intelFPGA_lite/18.1/quartus/eda/sim_lib/altera_mf.v(264) - but there is!!!
    
    tb.zip1 KB
ShengN_altera
Super Contributor
2 years ago
Hi,
I try the ROM-1 Port IP on both hex and mif files without any problem. Check the attached design file and screenshot inside. May be try with that attached design file and see got any problem or not?
Thanks,
Best Regards,
Sheng
rom_sim.zip8.6 MB
- NGord
  Occasional Contributor
  2 years ago
  Yours works even with Quartus 18.1 which is what I am using.
  The difference has to be I have a VHDL project and my ROM is part of the testbench file.
  I have to use a tcl script file to persuade Modelsim to compile the ROM first because of that.(tb.tcl)
  The issue has to be the vsim command or the fact I am using a MAX10.
  I attach my project.
  packet_parser.zip5 MB
ShengN_altera
Super Contributor
2 years ago
Hi,
I try to run the tb.tcl using modelsim ase from my side without any problem. Check attachments. May be that's bad installation of modelsim try to re-install again.
Thanks,
Regards,
Sheng
log.txt8 KB
- NGord
  Occasional Contributor
  2 years ago
  Now this is weird - I tried that it still didnt work.
  I even downloaded the Modelsim Starter from Quartus 20.1 - same version as you, but i get same fault.
  See attached transcript.
  Looks like you are running Linux and I am running Windows 10. Do you have a Windows machine?
  I f I were to try and learn Questa - it looks like I would need a license.
  Nigels_transcript.zip2 KB
  - NGord
    Occasional Contributor
    2 years ago
    Tried another laptop, Windows 10, same failure.
ShengN_altera
Super Contributor
2 years ago
Hi,
I tested with Window Modelsim Starter Edition without any problem as well check attached screenshots. After download and install modelsim, i run the tb.tcl.
Have you re-install modelsim to broadcast the environment changes?
Thanks,
Best Regards,
Sheng
NGord
Occasional Contributor
2 years ago
Yes I reinstalled Modelsim Starter edition 18.1 and tried version 20.1.
Where do we go from here?
I even went to the self service centre to get a free node locked license for Questa but the license didnt get recognised even though I set LM_LICENSE in the environmental variable. Thats another issue!
- NGord
  Occasional Contributor
  2 years ago
  I fixed it.. I deleted all versions of modelsim.ini and retried , now it works. Not sure what setting was making it go wrong though.
  Thanks for your help.