Forum Discussion

NGord's avatar
NGord
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Modelsim Lite Quartus 18.1 - simulating ROM

When simulating a ROM component within the testbench file (for generating a data packet) I get the Modelsim warning # ** Warning: (vsim-3473) Component instance "inst_altera_testbench_packet_rom : ...
Simulation
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,

I try the ROM-1 Port IP on both hex and mif files without any problem. Check the attached design file and screenshot inside. May be try with that attached design file and see got any problem or not?

Thanks,

Best Regards,

Sheng

  • NGord's avatar
    NGord
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Yours works even with Quartus 18.1 which is what I am using.
    The difference has to be I have a VHDL project and my ROM is part of the testbench file.
    I have to use a tcl script file to persuade Modelsim to compile the ROM first because of that.(tb.tcl)
    The issue has to be the vsim command or the fact I am using a MAX10.
    I attach my project.